Silicon carbide (that will be referred to as SiC) has a wide band gap, and its maximum breakdown electric field is larger than that of silicon by one order of magnitude. Thus, SiC has been highly expected to be used as a material for power semiconductor devices in the next generation. Up to the present, various types of electron devices, in particular, those for switching large power at high temperatures, have been developed, using single-crystal wafers, such as 4H--SiC and 6H--SiC. These crystals are alpha-phase SiC in which a zinc-blend structure and a wurtzite structure are superposed on each other. Also, semiconductor devices have been fabricated using crystals of beta-phase SiC, such as 3C--SiC.
Recently, power devices, such as Schottky diodes, vertical MOSFET and thyristors, and CMOS-IC as the most popular semiconductor devices, have been fabricated using SiC as a semiconductor material, and it has been confirmed that these devices exhibit far better characteristics than conventional Si semiconductor devices.
FIG. 9 is a cross-sectional view showing one example of power JFET that has been reported. In the JFET of FIG. 9, an n drift layer 11b is laminated on an n.sup.+ drain layer 11a, and a p.sup.+ embedded region 12 is formed in the n drift layer 11b by implanting ions at a high accelerating-field voltage. An n channel region 20 is formed by introducing n-type impurities into the n drift layer 11b located above the p.sup.+ embedded region 12, and p gate region 14 and n.sup.+ source region 13 are formed in a surface layer of the n channel region 20. A source electrode 17 is formed in contact with the n.sup.+ source region 13, and a drain electrode 18 is formed in contact with the n.sup.+ drain layer 11a, while a gate electrode 16 is formed in contact with the p gate region 14. A gate insulating film 15 is formed on the surface of the n channel region 20 interposed between two n.sup.+ source regions 13, and cooperates with the gate electrode 16 to provide a MOS gate. The source electrode 17 is in contact with not only the n.sup.+ source region 13 but also a p.sup.+ contact region 12a that is in contact with the p.sup.+ embedded region 12.
The n channel region 20 is interposed between the p.sup.+ embedded region 12 and the p gate region 14. When a positive voltage is applied to the gate electrode 16, an accumulation layer in which carriers are accumulated is induced in a portion of the n channel region 20 located below the gate insulating film 15, thus allowing current to flow from the drain electrode 18 to the source electrode 17. When a negative voltage is applied to the gate electrode 16, a depletion layer spreads out from the p gate region 14 into the n channel region 20, thereby to narrow a conduction region of the n channel region 20, and thus control current flow between the source electrode 17 and the drain electrode 18. Thus, the JFET of FIG. 9 is capable of switching current between the source and the drain, with a positive or negative voltage applied to the gate electrode 16.
While the JFET having the structure of FIG. 9 exhibits mostly favorable characteristics, it still needs to be improved in the following two aspects.
Firstly, there is always a demand for an increase in the gain with respect to gate voltage. Secondly, if the potential of the p gate region 14 becomes lower than that of the p.sup.+ embedded region 12, holes or current flow from the p.sup.+ embedded region 12 into the p gate region 14. As a result, the device tends to be turned on by mistake.
In the JFET of FIG. 9, the impurity concentration is controlled by, for example, implanting ions over the entire area of the n channel region 20, for the purpose of controlling switching characteristics. In this case, however, the n channel region 20 may affect spreading of a depletion layer between the p gate region 14 and the n drift layer 12, thus limiting control of the breakdown voltage.